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Altera_Forum's avatar
Altera_Forum
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9 years ago

Newcomer to VHDL, need help with debugging

Ok so I started learning VHDL about two months ago or so and recently I was handed the following code:

https://pastelink.net/1xvg

I kinda know what it does as the case statement of "contador" is easy to understand. Problem is I dunno what the "process(clock)" does nor how it contributes to the execution of the code.

Could somebody explain/debug it to me?

As far as I know I can divide the code into 3 blocks, the first one would have "rising edge (clock)" as signal entrance and would send CLK2 to the second block. The second block would send "contador" to the third block and that one would interact with the display/Raspberry.

PD: "Contador" is the word for counter in Spanish btw :p.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Did you try to run any simulation?

    Process which are you asking for, just generates slower clock.

    clock is an input clock. Signal clkdiv works as a counter here: 

    
 clkdiv<=clkdiv+"0000000000001";

    With every new clock cycle, clkdiv is increased by 1.

    For every other value of clkdiv than 0, clk2 is '0'. When clkdiv is bigger than "0000000001000", it is again set to 0 and one cycle later, clk2 is set to '1', but only for one cycle of clock: 

    
 if clkdiv="0000000000000" then 
   clk2 <= '1';
 else
   clk2<= '0'; 
 end if;
 if clkdiv > "0000000001000" then
   clkdiv<="0000000000000";
 end if;

    And then clk2 is used as a clock in other process... 

    
process(clk2)
begin
if(rising_edge(clk2)) then

    Is the answer ok for you?

    Regards,

    kolas
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

     	if(rising_edge(clock)) then 
	
		if clkdiv="0000000000000" then  
			clk2 <= '1';
		else
			clk2<= '0'; 
		end if; </code>

    Ok, so this part is the one that decides which value of clk2 is sent to the other process. Go it. Thanks.

    Just one question, how does an input clock's signal work? I suppose it has a frequency in which it changes from 1 to 0 and when it changes to 1 the rising edge returns a true as if it was a boolean, am I right?

    PD: I have not done a simulation because I am still having problems with the installation of the Xilinx ISE.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    Just one question, how does an input clock's signal work? I suppose it has a frequency in which it changes from 1 to 0 and when it changes to 1 the rising edge returns a true as if it was a boolean, am I right?

    --- Quote End ---

    Generally yes. At input you have rectangular signal with given frequency. Function rising_edge returns boolean.

    Remember only, that this code creates hardware, so basically by using rising_edge function you are generating registers etc...

    Regards,

    kolas
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    These are very basic questions that are answered in a Digital Logic text book and VHDL text book/tutorial. Your questions make it appear you think VHDL is like a software language - it is not. It is a hardware description language. It describes a circuit made out of gates and registers. Code is not executed like software programming, all processes in all entities run in parallel.

    Also - Xilinx ISE is the compiler for Xilinx devices. This is an altera forum (Xilinx's Competitor). If you need help with ISE, you need to visit the Xilinx forums.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    PD: "Contador" is the word for counter in Spanish btw :p.

    --- Quote End ---

    and the name of a cyclist...alberto contador i believe