Newcomer to VHDL, need help with debugging

Did you try to run any simulation?

Process which are you asking for, just generates slower clock.

clock is an input clock. Signal clkdiv works as a counter here:

 clkdiv<=clkdiv+"0000000000001";

With every new clock cycle, clkdiv is increased by 1.

For every other value of clkdiv than 0, clk2 is '0'. When clkdiv is bigger than "0000000001000", it is again set to 0 and one cycle later, clk2 is set to '1', but only for one cycle of clock:

 if clkdiv="0000000000000" then 
   clk2 <= '1';
 else
   clk2<= '0'; 
 end if;
 if clkdiv > "0000000001000" then
   clkdiv<="0000000000000";
 end if;

And then clk2 is used as a clock in other process...

process(clk2)
begin
if(rising_edge(clk2)) then

Is the answer ok for you?

Regards,

kolas