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Altera_Forum
Honored Contributor
Honored ContributorNewcomer to VHDL, need help with debugging
Ok so I started learning VHDL about two months ago or so and recently I was handed the following code: https://pastelink.net/1xvg I kinda know what it does as the case statement of "contad...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Just one question, how does an input clock's signal work? I suppose it has a frequency in which it changes from 1 to 0 and when it changes to 1 the rising edge returns a true as if it was a boolean, am I right? --- Quote End --- Generally yes. At input you have rectangular signal with given frequency. Function rising_edge returns boolean. Remember only, that this code creates hardware, so basically by using rising_edge function you are generating registers etc... Regards, kolas