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Altera_Forum's avatar
Altera_Forum
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9 years ago

Newcomer to VHDL, need help with debugging

Ok so I started learning VHDL about two months ago or so and recently I was handed the following code: https://pastelink.net/1xvg I kinda know what it does as the case statement of "contad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

 	if(rising_edge(clock)) then 
	
		if clkdiv="0000000000000" then  
			clk2 <= '1';
		else
			clk2<= '0'; 
		end if; </code>

Ok, so this part is the one that decides which value of clk2 is sent to the other process. Go it. Thanks.

Just one question, how does an input clock's signal work? I suppose it has a frequency in which it changes from 1 to 0 and when it changes to 1 the rising edge returns a true as if it was a boolean, am I right?

PD: I have not done a simulation because I am still having problems with the installation of the Xilinx ISE.