Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow by referring to quartus document i solved those by analysing in time quest timing analyzer. If i look at "Unconstrained paths Summary" in timing analyzer there are unconstrained clock, unconstrained input port, unconstrained input port path, unconstrained output port and unconstrained output port path. From the quartus document i came to know that these things can be solved by setting input delay and output delay, but i dont know how to calculate those delays because this is occuring when modules are interconnected. How can i solve this? Any help is appreciated. Thank you

Generally, you should know the board trace delay and the timing parameter of downstream/upstream device. You could give the detail description in TQ handbook and example in TQ cookbook. You could search these doc on altera web

Thank you for the reply. I will have a look at the document. Whether the method what i am following is right? am i in the right way?

--- Quote Start --- Thank you for the reply. I will have a look at the document. Whether the method what i am following is right? am i in the right way? --- Quote End --- Hi, be aware that the input delay and output delay only descripts the timing for the FPGA to the outside world. Timing violations between verilog modules will not be affected by this settings. If you have internal holdtime violations look to the clock generation. Do you have gated clocks or clocks generated by a ripple counter in your design ? Kind regards GPK

Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations. Q> Do you have gated clocks or clocks generated by a ripple counter in your design ? A> Yes i have clocks generated by ripple counter. Most of the times i have used PLL megafunction, other times i cannot use PLL megafunction to generate clocks of lower frequency. So i have used counter to generate clock.

--- Quote Start --- Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations. Q> Do you have gated clocks or clocks generated by a ripple counter in your design ? A> Yes i have clocks generated by ripple counter. --- Quote End --- Hi, with a ripple counter you add always a small delay to the next clock stage. If you have in your design paths between the different clock domains you will run into holdtime violation. Why not replace the ripple counter with a binary counter ? Kind regards GPK

Newbie question about SDC in Timing analyzer

14 Replies

Altera_Forum
Honored Contributor
15 years ago
Thank you for the info.

I need a confirmation about unconstrained clocks.

I have created system clock by using create_clock and create_generated_clock.
As rbugalho said there are unconstrained clocks but the Target where
its showing are the modules where i am just using the system clock, it has nothing to do with clock generation.

How to solve that problem?
Is it again related to create_clock or create_generated_clock?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Thank you for the info.

I need a confirmation about unconstrained clocks.

I have created system clock by using create_clock and create_generated_clock.
As rbugalho said there are unconstrained clocks but the Target where
its showing are the modules where i am just using the system clock, it has nothing to do with clock generation.

How to solve that problem?
Is it again related to create_clock or create_generated_clock?
--- Quote End ---

Hi,

you have to evaluate the unconstrainted "clocks" carefully. Are they really clocks or gate signals for some other clocks ? If these are independent clock you have to use the create-clock, if they are derived from other clocks use create_generated_clock. BTW

In timequest you can generate a Clock transfer Report. In this report you will find all your paths between your clock domains. Check if some of the pathe are false paths.

Kind regards

GPK
Altera_Forum
Honored Contributor
15 years ago
Blackpulsor,

from my experience, the unconstrained clocks you are seeing in the report are ripple or gated clocks, generated somewhere in your design, that you have not constrained.
The STA will automatically notice that these signals are being used as clocks but that you have not defined their constraints.

Are you sure your modules are not generating ripple clocks or gating clocks inside those modules?

If this is the case, you're missing a create_generate_clock blabla for each of those cases.
Altera_Forum
Honored Contributor
15 years ago
Thank you for all the valuable suggestions.
Considering the above things, i rechecked and finally
i solved the issue.

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Newbie question about SDC in Timing analyzer

14 Replies

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