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Altera_Forum
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15 years ago

Newbie question about SDC in Timing analyzer

Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow b...
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Altera_Forum
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15 years ago

Thank you for the info.

I need a confirmation about unconstrained clocks.

I have created system clock by using create_clock and create_generated_clock.

As rbugalho said there are unconstrained clocks but the Target where

its showing are the modules where i am just using the system clock, it has nothing to do with clock generation.

How to solve that problem?

Is it again related to create_clock or create_generated_clock?