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Altera_Forum
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15 years ago

Newbie question about SDC in Timing analyzer

Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow b...
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Altera_Forum
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15 years ago

Blackpulsor,

from my experience, the unconstrained clocks you are seeing in the report are ripple or gated clocks, generated somewhere in your design, that you have not constrained.

The STA will automatically notice that these signals are being used as clocks but that you have not defined their constraints.

Are you sure your modules are not generating ripple clocks or gating clocks inside those modules?

If this is the case, you're missing a create_generate_clock blabla for each of those cases.