Neuron implementation in VHDL (code attached)

There are several problems with this code:

1. The first part of the code isnt in a process.

2. the calculation parts are not synchronous (this mens they will work very slowly)

3. There is no output

This code is clearly incomplete. I suggest you complete it, write a testbench and see if it functions correctly.

Thank you very much for your corrections.

Could you suggest me how to guarantee that all process are synchronous?

maybe if I test the rise edge in the input CLK for all process?

Thanks,

Hello dear,

I took an example from a book (commented in code) and I made some modifications.

The code (attached) model a layer with three neurons in which I am intending to make a component and create a neural network from it later.

The code was compiled and is syntactically correct.

My doubt is about this piece of code, where there is a shift register operation:

-- shift register inference.

if(clk'event and clk='1') then

weight:= w & weight(1 to n*m-1);

end if;

That logical AND operation between the input vector of bits 'w' (assuming that it is considered to be a vector of bits) and the 'weight' array of type 'w', is to be considered occurring between 'w' and all elements of 'weight' inside the 'if' statement?

Or just between the first elemente of 'weight'?

Sorry if this doubt could seem simple, I am comming from languages like C/java.

I am looking for a intuitive explanation about this shifting register operation. It seems to differ from the logical n-bits shifting which I know.

thanks,

Lots of problems with the code. You can clearly see you've come from a C/Java background

I suggest starting again, as the style of the code is not suitable for FPGA implementation. HDL stands for hardware description language. Your code doesnt look like its going to produce any useful hardware. I suggest starting again - start with a peice of paper and draw your circuit. How do you expect to write the code if you dont know roughly what the circuit should be? Only then should you write the HDL.

Forget all your C/Java skills for now. VHDL is completly different.

And Note: & is concatenate in VHDL, not a logical operator.

Since you cited to start from a piece of paper, I could'nt spend my chance to show my drawing abilities (attached)... so

The code I sent the last post is just my try to make a component for a global entity referred as the ANN entity in the drawing.

So the entity nn_layer has no meaning for itself, but if it will be a component for a global entity, does it make sense based on my drawing?

Each nn_layer represents a set of 3 neurons in which we have the same x1,x2 and x3 as inputs for each of neuron.

As neurons, we can think of a sigmoid function of the outputs y1,y2 and y3, which I will implemente after, because it does not affect the architecture of the problem. The sigmoid will be implemented (aproximated) as lookup table.

Before that inputs x1,x2, and x3 are presented to the neurons (sigmoids) they are multiplied by their respectives and uniques 'w's loaded from the ROM.

These yn outputs are passed from one nn_layer entity to the nexts nn_entity. I need 3 nn_layer entities in total.

These 3 nn_layer entities will be modeled as one unique entity (ANN) tha will control the ROM access and provide clock.

The mux are irrelevant and will convert serial to paralell information from the external.

I attached another figure from the book, it is very intuitive and use the variables names that I am using in the code. I is a nn_layer representation.

Thank you very much for your patience and help.