Altera_ForumHonored Contributor12 years agoNeuron implementation in VHDL (code attached) Hi all.I am just learning VHDL and as an exercise, I am trying to model a neuron in VHDL (attached the code). The neuron has three inputs, three weights and one threshold value (as entity inputs).T...Show Moreneuron.vhd2 KB
Altera_ForumHonored Contributor12 years agoYes. Using the rising edge of clk is the way synchronous design works
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