Nested SystemVerilog/Verilog Include Files

Hi,

I am importing a SystemVerilog project into a Cyclone 10GX using Quartus Pro 21.2, but unfortunately I am getting some issues.

This project has include files to define various parameters. One of the include files includes another include file at the top. This is where I think I am getting an issue.

To me it looks like it may be evaluating the include file that has another include file in it before evaluating the include file that it relies on. I have made a small dummy project that illustrates the issue and get the following error:

Error(13406): Verilog HDL error at parameters.vh(1): object "param_t" is not declared 

Is there a way to control the order in which include files are evaluated? Currently I add the include files using the following command in my tcl script:

set_global_assignment -name SEARCH_PATH "../../include"

I have attached the small project. To create the project it I go to /nested_include_test/cyclone10_gx then run

quartus_sh -t nested_include_test.tcl

in Linux. The project file will then be in the work folder below.

Thanks

David