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david_'s avatar
david_
Icon for New Contributor rankNew Contributor
4 years ago
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Nested SystemVerilog/Verilog Include Files

Hi, I am importing a SystemVerilog project into a Cyclone 10GX using Quartus Pro 21.2, but unfortunately I am getting some issues. This project has include files to define various parameters. On...
  • Nurina's avatar
    Nurina
    4 years ago

    Hi,


    I think the problem is the fact that you declared a typedef in a header file. Because they're usually declared in a verilog HDL file before the module declaration, but I don't think that's what you want to do.


    Header files are problematic in general, which is why SystemVerilog introduced us to packages: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6469140

    You should use packages instead of `include. You can populate packages with parameters too.


    Regards,

    Nurina


david_'s avatar
david_
Icon for New Contributor rankNew Contributor
4 years ago

Hi Nurina, ok thanks Il convert it to a package. It is a Xilinx project that I am importing and works there.

Regards

David

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!