Nested SystemVerilog/Verilog Include Files

Hi,

I think the problem is the fact that you declared a typedef in a header file. Because they're usually declared in a verilog HDL file before the module declaration, but I don't think that's what you want to do.

Header files are problematic in general, which is why SystemVerilog introduced us to packages: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6469140

You should use packages instead of `include. You can populate packages with parameters too.

Regards,

Nurina