Forum Discussion
New ContributorNested SystemVerilog/Verilog Include Files
Hi,
I think the problem is the fact that you declared a typedef in a header file. Because they're usually declared in a verilog HDL file before the module declaration, but I don't think that's what you want to do.
Header files are problematic in general, which is why SystemVerilog introduced us to packages: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6469140
You should use packages instead of `include. You can populate packages with parameters too.
Regards,
Nurina
Regular ContributorHi,
This KDB teaches how you can use parameters in header files: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07231998_9862.html
Also make sure you set the correct Verilog version, typedef is SystemVerilog not Verilog.
Regards,
Nurina
New ContributorHi,
Unfortunately the KDB did not help me. I changed the build script to include
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2012
but that didn't remove the error.
I have attached the project as it stands if it would be possible for you to have a look? It has not really changed from the first post, apart from having the SystemVerilog flag. It is run in the same way.
Thanks
David
- david_
Maybe it could be something to do with this warning?
Warning(16847): Verilog HDL warning at parameters.vh(8): concatenation member label not yet supported; label ignored
