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david_'s avatar
david_
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5 years ago
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Nested SystemVerilog/Verilog Include Files

Hi, I am importing a SystemVerilog project into a Cyclone 10GX using Quartus Pro 21.2, but unfortunately I am getting some issues. This project has include files to define various parameters. On...
  • Nurina's avatar
    Nurina
    5 years ago

    Hi,


    I think the problem is the fact that you declared a typedef in a header file. Because they're usually declared in a verilog HDL file before the module declaration, but I don't think that's what you want to do.


    Header files are problematic in general, which is why SystemVerilog introduced us to packages: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6469140

    You should use packages instead of `include. You can populate packages with parameters too.


    Regards,

    Nurina


david_'s avatar
david_
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5 years ago

Hi,

Unfortunately the KDB did not help me. I changed the build script to include

set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2012

but that didn't remove the error.

I have attached the project as it stands if it would be possible for you to have a look? It has not really changed from the first post, apart from having the SystemVerilog flag. It is run in the same way.

Thanks

David

david_'s avatar
david_
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5 years ago

Maybe it could be something to do with this warning?

Warning(16847): Verilog HDL warning at parameters.vh(8): concatenation member label not yet supported; label ignored