Need help with my final project design (Ethernet Transmitter)

1. I assume you mean for simulation? File IO is not synthesisable. Either way, you should know the size of your vector in runtime. When you issue a read command it will try and fit the text to the vector.

Why not post some example code so we can try and understand what you're trying to do...

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1. I assume you mean for simulation? File IO is not synthesisable. Either way, you should know the size of your vector in runtime. When you issue a read command it will try and fit the text to the vector.

Why not post some example code so we can try and understand what you're trying to do...

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Thank you for your answer.

I didn't write any code yet, because I still don't know how to get the input. I thought to get the input from a TEXT file but you just told me that I can't synthesize it, thank you for that.

I can divide that Ethernet frame to 3 parts:

1. DATA LINK - 18 Bytes

2. Payload (DATA) - 46-1500 Bytes

3. CRC - 4 Bytes

and use FIFO storage for each one of them (in addition to module that I will write to fill up the FIFO before starting the system).

My question is how to build the second FIFO storage in the Byte's range in dynamical? It will limit my DATA to be a constant width.

What do you think about it? and how can I solve the problem with the dynamical width of std_logic_vector?

Is there any option to create a storage for 1500 bytes?

What interface are you planning on using? the packets will not arrive all in one go, they will arrive at a rate of 1 dword (being the width of the interface) per clock, (or multiple clocks)

Eg. for axi streaming you will receive 32 or 64 bits/ clock (depending on what interface size you chose). There are a few sideband signals to tell you things like whether the dword is valid or whether its the last dword in the packet. It is then up to you to decode the header.

You need to think like a hardware engineer. Your interfaces are always a fixed size - never dynamic.

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What interface are you planning on using? the packets will not arrive all in one go, they will arrive at a rate of 1 dword (being the width of the interface) per clock, (or multiple clocks)

Eg. for axi streaming you will receive 32 or 64 bits/ clock (depending on what interface size you chose). There are a few sideband signals to tell you things like whether the dword is valid or whether its the last dword in the packet. It is then up to you to decode the header.

You need to think like a hardware engineer. Your interfaces are always a fixed size - never dynamic.

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You are very helpful.

I want to understand how to implement it before I start writing.

I have to decide on an interface? Can't I decide that I fill up the FIFO stacks Ethernet Frame /per clock ? (as I worte before, I will create a few FIFO stacks).

Then, as pipeline works, I will connect all the models with D-FLIP-FLOP between them, and I will pass the information in the FIFO stacks to the next segments with registers. When I execute whatever I need to between the segments. Can it work?

My problem is that I am pretty good with writing codes with Python/C/C++/MATLAB, and I understand that writing with VHDL is different, I feel like I don't know about alot of options that the language offers. Can you suggest for a good and quick guide?

There is no quick guide. And knowing software languages will be of little help to you.

You cannot just send an entire ethernet frame/clock with some random flip flops around.

I highly suggest you find a textbook about digital logic, and then when you understand that - find a VHDL tutorial. This is NOTHING like writing software.

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There is no quick guide. And knowing software languages will be of little help to you.

You cannot just send an entire ethernet frame/clock with some random flip flops around.

I highly suggest you find a textbook about digital logic, and then when you understand that - find a VHDL tutorial. This is NOTHING like writing software.

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Hi Tricky, I know digital logic and I already designed circuits in the past.

I don't understand why I can't send entire ethernet frame per clock? Let me try to explain myself better:

I am planning to use/write:

1. load input to 3 FIFO stacks (maybe create a quick GUI with MATLAB for this).

2. Add VLAN and priority if needed (802.1 model).

3. create CRC model

4. Assembly the ethernet frame model.

5. Transmite model.

Yes, I still don't know how to start, and that's why I want to understand my limits and possibilities with the FPGA.

why can I pass 4 bits in one clock and why I can't pass 1500 bytes in one clock? - I don't want to do anything with these 1500 Bytes besides assembly them together at the end. (isn't it depended on the size of the register?)

also, I don't understand how can I design a control unit?

Thanks Tricky!

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Hi Tricky, I know digital logic and I already designed circuits in the past.

I don't understand why I can't send entire ethernet frame per clock? Let me try to explain myself better:

I am planning to use/write:

1. load input to 3 FIFO stacks (maybe create a quick GUI with MATLAB for this).

2. Add VLAN and priority if needed (802.1 model).

3. create CRC model

4. Assembly the ethernet frame model.

5. Transmite model.

Yes, I still don't know how to start, and that's why I want to understand my limits and possibilities with the FPGA.

why can I pass 4 bits in one clock and why I can't pass 1500 bytes in one clock? - I don't want to do anything with these 1500 Bytes besides assembly them together at the end. (isn't it depended on the size of the register?)

also, I don't understand how can I design a control unit?

Thanks Tricky!

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You can pass 1500 bytes in 1 clock if you like, but you have no way of getting it off the chip - it wont have that many pins. You transmit all packets 1 dword at a time, and similarly you will receive it 1 dword at a time.

Are you using the altera ethernet core? what external interfaces are you using? what phy are you using? what FPGA is it?

Your answers show your digital design knowledge are somewhat lacking - please go and study.