Need help with my final project design (Ethernet Transmitter)

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There is no quick guide. And knowing software languages will be of little help to you.

You cannot just send an entire ethernet frame/clock with some random flip flops around.

I highly suggest you find a textbook about digital logic, and then when you understand that - find a VHDL tutorial. This is NOTHING like writing software.

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Hi Tricky, I know digital logic and I already designed circuits in the past.

I don't understand why I can't send entire ethernet frame per clock? Let me try to explain myself better:

I am planning to use/write:

1. load input to 3 FIFO stacks (maybe create a quick GUI with MATLAB for this).

2. Add VLAN and priority if needed (802.1 model).

3. create CRC model

4. Assembly the ethernet frame model.

5. Transmite model.

Yes, I still don't know how to start, and that's why I want to understand my limits and possibilities with the FPGA.

why can I pass 4 bits in one clock and why I can't pass 1500 bytes in one clock? - I don't want to do anything with these 1500 Bytes besides assembly them together at the end. (isn't it depended on the size of the register?)

also, I don't understand how can I design a control unit?

Thanks Tricky!