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What interface are you planning on using? the packets will not arrive all in one go, they will arrive at a rate of 1 dword (being the width of the interface) per clock, (or multiple clocks)
Eg. for axi streaming you will receive 32 or 64 bits/ clock (depending on what interface size you chose). There are a few sideband signals to tell you things like whether the dword is valid or whether its the last dword in the packet. It is then up to you to decode the header.
You need to think like a hardware engineer. Your interfaces are always a fixed size - never dynamic.
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You are very helpful.
I want to understand how to implement it before I start writing.
I have to decide on an interface? Can't I decide that I fill up the FIFO stacks Ethernet Frame /per clock ? (as I worte before, I will create a few FIFO stacks).
Then, as pipeline works, I will connect all the models with D-FLIP-FLOP between them, and I will pass the information in the FIFO stacks to the next segments with registers. When I execute whatever I need to between the segments. Can it work?
My problem is that I am pretty good with writing codes with Python/C/C++/MATLAB, and I understand that writing with VHDL is different, I feel like I don't know about alot of options that the language offers. Can you suggest for a good and quick guide?
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