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Hi Tricky, I know digital logic and I already designed circuits in the past.
I don't understand why I can't send entire ethernet frame per clock? Let me try to explain myself better:
I am planning to use/write:
1. load input to 3 FIFO stacks (maybe create a quick GUI with MATLAB for this).
2. Add VLAN and priority if needed (802.1 model).
3. create CRC model
4. Assembly the ethernet frame model.
5. Transmite model.
Yes, I still don't know how to start, and that's why I want to understand my limits and possibilities with the FPGA.
why can I pass 4 bits in one clock and why I can't pass 1500 bytes in one clock? - I don't want to do anything with these 1500 Bytes besides assembly them together at the end. (isn't it depended on the size of the register?)
also, I don't understand how can I design a control unit?
Thanks Tricky!
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You can pass 1500 bytes in 1 clock if you like, but you have no way of getting it off the chip - it wont have that many pins. You transmit all packets 1 dword at a time, and similarly you will receive it 1 dword at a time.
Are you using the altera ethernet core? what external interfaces are you using? what phy are you using? what FPGA is it?
Your answers show your digital design knowledge are somewhat lacking - please go and study.
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