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1. I assume you mean for simulation? File IO is not synthesisable. Either way, you should know the size of your vector in runtime. When you issue a read command it will try and fit the text to the vector.
Why not post some example code so we can try and understand what you're trying to do...
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Thank you for your answer.
I didn't write any code yet, because I still don't know how to get the input. I thought to get the input from a TEXT file but you just told me that I can't synthesize it, thank you for that.
I can divide that Ethernet frame to 3 parts:
1. DATA LINK - 18 Bytes
2. Payload (DATA) - 46-1500 Bytes
3. CRC - 4 Bytes
and use FIFO storage for each one of them (in addition to module that I will write to fill up the FIFO before starting the system).
My question is how to build the second FIFO storage in the Byte's range in dynamical? It will limit my DATA to be a constant width.
What do you think about it? and how can I solve the problem with the dynamical width of std_logic_vector?
Is there any option to create a storage for 1500 bytes?
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