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Altera_Forum's avatar
Altera_Forum
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17 years ago

Multiple Avalon MM Master read/write access problem

Hello All,

I have designed a simple two port double frame buffer.

1. Avalon MM burst read.

2.Avalon MM burst write.

The Avalon mm burst write and read both keep switching Buffer locations in order to make sure a buffer is only read or written at a time.

When both Buffers are set within one Sram chip the system seems to give corrupt data

All the logic has been checked multiple times and there is no time when the two buffers are read and written at the same time, however yet I tend to get corrupt data.

However when one buffer is configured in ddr ram and the other in sram , the frame buffer seems to work perfectly fine with no corrupt data.

Seems like a arbitration problem, which i thought sopc is suppose to take care of.... Any ideas???

thanks nadeem

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    1 - Could be an addressing problem on your part. Are you perhaps incrementing your address by larger amounts than you expect? This might make the first frame buffer run into the second but not vice-versa.

    2 - Have you simulated?

    3 - I also have a frame buffer that supports bursting and the Altera VIP packets so I have some experience in the matter. If you don't object to posting your code, I could glance at yours and see if anything obvious jumps out.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    4 - Are you properly honoring the waitrequest on the write side?

    5 - Are you properly using the readdatavalid signal?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    1 - Is there any case you can think of where the write buffer and read buffer would be the same?

    2 - Is there any pattern to the video corruption (losing pixels, gaining pixels, etc.) that might provide a clue?

    I'm going through the code now.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Jake thanks for you reply,

    The only clue I have is that the data is More currupted in the first part of the frame (field 1). While field two is currupted but still visible.

    Basicaly the Buffer writes one 720 * 243 Frame, then the read part reads the buffer twice ( to make up field one and two 720*486)

    As during field 1 Both Read and Write are acessing the memmory controller, i am assuming it is some sort of arbitration problem.

    What do u think?

    thanking you,

    Nadeem jamal
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Well I'm not a native VHDL speaker so you may have to clarify some things for me. I'm looking at your control state machine. I'm gong to make the assumption that you are normally only operating in the "idle", "Triggered", and "StartBuffering" states.

    Here is my understanding of what I'm seeing...

    1 - You wait in "idle" until you receive a command through the control port which writes a value into "sig_frameBuffer_reg" of 0x81 at which point you move into the "StartBuffering" state. As a note, I don't ever see you initialize "var_switch" to 0 but maybe that's intrinsic.

    2 - In the "StartBuffering" state, the first time, you initialize both a read and a write transfer then move to the "Triggered" stage for the purpose of disabling your sig_Start_Read and sig_Start_Write signals.

    3 - Now you oscillate between "idle" and "StartBuffering" until both your read and write controllers indicate they have finished their transfers. At which point, in the "StartBuffering" state you swap the frame addresses and initialize another write and another read transfer. So I have to assume that your field repetition is being done in the "Source" module.

    I don't see any issues with this part so my guess is that it's further down. Is my understanding correct to this point?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes Jake that is right, your understanding seems fine..

    Hmm your right i don't really init var_switch, but i guess it automatically becomes 0 when the state switches to Start buffering.

    Yes Depending on Framebuffer_reg i determine which mode to be in. and if mode has not changed i continue toggling between Idle and start buffering.

    Yes Triggerd state is just to disable the

    sig_Start_Read

    sig_Start_Write

    And yes the Source module gives

    Data_Read_Complete signal only after both fields are read.

    nadeem
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Jake any new Ideas:(

    Please let me know when you have the time , my due date is day after tom and this is the last part.

    Thanks allot

    regards nadeem