Multiple Avalon MM Master read/write access problem

Well I'm not a native VHDL speaker so you may have to clarify some things for me. I'm looking at your control state machine. I'm gong to make the assumption that you are normally only operating in the "idle", "Triggered", and "StartBuffering" states.

Here is my understanding of what I'm seeing...

1 - You wait in "idle" until you receive a command through the control port which writes a value into "sig_frameBuffer_reg" of 0x81 at which point you move into the "StartBuffering" state. As a note, I don't ever see you initialize "var_switch" to 0 but maybe that's intrinsic.

2 - In the "StartBuffering" state, the first time, you initialize both a read and a write transfer then move to the "Triggered" stage for the purpose of disabling your sig_Start_Read and sig_Start_Write signals.

3 - Now you oscillate between "idle" and "StartBuffering" until both your read and write controllers indicate they have finished their transfers. At which point, in the "StartBuffering" state you swap the frame addresses and initialize another write and another read transfer. So I have to assume that your field repetition is being done in the "Source" module.

I don't see any issues with this part so my guess is that it's further down. Is my understanding correct to this point?

Jake