Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Multiple Avalon MM Master read/write access problem

Hello All, I have designed a simple two port double frame buffer. 1. Avalon MM burst read. 2.Avalon MM burst write. The Avalon mm burst write and read both keep switching Buffer lo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes Jake that is right, your understanding seems fine..

Hmm your right i don't really init var_switch, but i guess it automatically becomes 0 when the state switches to Start buffering.

Yes Depending on Framebuffer_reg i determine which mode to be in. and if mode has not changed i continue toggling between Idle and start buffering.

Yes Triggerd state is just to disable the

sig_Start_Read

sig_Start_Write

And yes the Source module gives

Data_Read_Complete signal only after both fields are read.

nadeem