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mappy5's avatar
mappy5
Icon for New Contributor rankNew Contributor
4 years ago

Module removal by compilation optimization

I want to synthesize soft CPU IP by itself and evaluate resources.

I created a TOP wrapper to implement a CPU module.
However, when I look at the compilation result, I can't find the CPU module I implemented.
When I check the Registers Removed During Synthesis in the compile log, I see a lot of registers.

I tried the option to disable optimization, but it didn't work.
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF

Is there any other way to prevent the module from being removed by compilation optimization?

8 Replies

  • skyjuice's avatar
    skyjuice
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Which Quartus version are you using? The latest 21.3 has a new report called 'Hierarchies Optimized Away During Sweep" that includes the details on what is optimized away alongside with the reasons.

    • mappy5's avatar
      mappy5
      Icon for New Contributor rankNew Contributor
      4 years ago

      hi skyjuice

      Quartus version :20.3 build 158 pro edition

      I will install 21.3 and try it.

    • mappy5's avatar
      mappy5
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi

      There are 3147400 deleted registers.

      Do I need to add a pragma to Verilog for everything?

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        Is your design or this soft CPU you mention (Nios?) not connected to any I/O? That is a lot getting optimized away. What does the report mentioned indicate?

        If you're not connected to I/O pins, add Virtual Pin assignments in the Assignments Editor to prevent unconnected logic from getting optimized away.

  • mappy5's avatar
    mappy5
    Icon for New Contributor rankNew Contributor
    4 years ago

    CPU was released by the 3rd vendor.

    I created a Top wrapper that outputs the IO of the CPU Top module to the FPGA pin.

    However, since the number of CPU IOs is large for FPGA pins, some inputs are input from registers.

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      4 years ago

      So can you answer the question I asked? What exactly does the report indicate is getting optimized away? And have you tried adding virtual pin assignments?

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi,


    Are you able to implement the synthesis attribute to avoid the register from being optimized?