Altera_Forum
Honored Contributor
Honored ContributorModular SGDMA Streaming
Hi,
I'm trying to stream data from an ADC to my DDR RAM. I’ve hit a roadblock with using the modular SGDMA core to do streaming to memory mapped transfers to DDR RAM. An interrupt that is supposed to go off when the transfer is complete never goes off. This isn’t because the data never stops being written but is actually because the data never begins to be written. I’ve noticed this because I print out some of the memory addresses during the wait for the interrupt -> the values that get written out don’t correspond to the values being fed into the SGDMA. I’ve noticed issues which point to either a software or hardware problem. The software issue is that the IOWR and IORD commands don’t seem to be working correctly. IOWR_32DIRECT(MEM_IF_DDR2_EMIF_0_BASE, testNumber, testNumber); IORD (MEM_IF_DDR2_EMIF_0_BASE, testNumber); /////////////////////////////////////////////////////////////^Doesn’t work memcpy(MEM_IF_DDR2_EMIF_0_BASE + testNumber*sizeof(int), &testNumber, sizeof(testNumber)); ->writing memcpy(&value, (MEM_IF_DDR2_EMIF_0_BASE+testNumber*sizeof(int)), sizeof(int)); ->reading ////////////////////////////////////////////////////////////^Works I’m not sure if this is because in my tests I am writing to RAM, I will look into that, but this is an issue since the data transfer descriptor is initialized using the IOWR_32DIRECT function. I don’t think this is the issue though because I’m able to call these same functions successfully when I do memory-mapped to memory-mapped data transfers. I've attached the c file that I'm using to test the streaming data transfer (main.c), the line that doesn't work is# 74: if (sgdma_interrupt_fired == 1) -> I've changed this to a while check and noticed that the interrupt never gets asserted. The next area that I think might be an issue is the way I collect data from the incrementing register (the one I’m streaming data from). I simply connected the bus streaming data bus to the streaming sink of the write master in the Qsys project. I have an image of that project with the connection circled (Qsys.png). Is that the correct way to connect streaming data to a Qsys project? Is there anything that’s obviously wrong with the way I’ve set up the connections? Any advice on how to approach figuring out why the interrupt I need doesn’t go off?
