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Altera_Forum
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10 years ago

Modular SGDMA Streaming

Hi, I'm trying to stream data from an ADC to my DDR RAM. I’ve hit a roadblock with using the modular SGDMA core to do streaming to memory mapped transfers to DDR RAM. An interrupt that is suppo...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Your image is so small it's difficult to see. Can you add a signaltap instance on the stream interface to check that anything is actually going through it?

As for your problem with the macros, it's probably because the 32DIRECT versions use a byte offset, while IORD/IOWR use a word offset. Therefore you either need to multiply testNumber by sizeof(int) in your line with IOWR_32DIRECT, or only use IOWR and IORD. This should probably work: 

IOWR(MEM_IF_DDR2_EMIF_0_BASE, testNumber, testNumber);
IORD (MEM_IF_DDR2_EMIF_0_BASE, testNumber);

Using direct addressing, either with pointers or memcpy work also, but you need to be careful if your CPU has a data cache. Then you need to flush or invalidate it before or after the operation.