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Altera_Forum's avatar
Altera_Forum
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11 years ago

Modelsim throws an error, but Quartus happily compiles VHDL code

I have a VHDL module containing statements like: 

control_ccassigns_6_D <= unsigned(WD)((WIDTH + START) - 1 downto START);

Modelsim flags these as: 

Vcom: Prefix of slice name cannot be type conversion (UNSIGNED)  expression.

But if Quartus II complies this without a blink ...

I know how to change the code to get rid of the error. My question is: is Modelsim right or wrong?

Regards,

Josy

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Modelsim is usually correct in these things. Quartus (and Xilinx) tend to just work without complaint.

    I could check the LRM for you?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    I could check the LRM for you?

    --- Quote End ---

    That's the spirit. I skimmed through the LRM, but that's not my kind of literature :)

    If it truly is an error, it is kind of funny that when we replace the unsigned cast by a function doing the exact same thing, Modelsim thinks it's fine. 

     
function slv2u( v : std_logic_vector) return unsigned is
    return unsigned(v) ;
end function;
control_ccassigns_6_D <= slv2u(WD)((WIDTH + START) - 1 downto START);
    doest the trick.

    Regards,

    Josy
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Tricky,

    did you find a moment to check the LRM about this?

    Regards,

    Josy
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Sorry - no. Ill have a look tomorrow if I remember (its on my work laptop).