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Altera_Forum's avatar
Altera_Forum
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11 years ago

Modelsim throws an error, but Quartus happily compiles VHDL code

I have a VHDL module containing statements like: control_ccassigns_6_D <= unsigned(WD)((WIDTH + START) - 1 downto START); Modelsim flags these as: Vcom: Prefix of slice name cannot be t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I could check the LRM for you?

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That's the spirit. I skimmed through the LRM, but that's not my kind of literature :)

If it truly is an error, it is kind of funny that when we replace the unsigned cast by a function doing the exact same thing, Modelsim thinks it's fine. 

 
function slv2u( v : std_logic_vector) return unsigned is
    return unsigned(v) ;
end function;
control_ccassigns_6_D <= slv2u(WD)((WIDTH + START) - 1 downto START);
doest the trick.

Regards,

Josy