Modelsim Fatal error: "TOO MANY PORT CONNECTONS" Help me!

Hi guys:

/* Altered System module for testbench. */
module System(DIN, Reset, PB, clock, WR_MEM_out, ADDR_out, DOUT_out, DONE, IR_out, R0_out, R1_out, R2_out, R3_out, R4_out, R5_out, R6_out, R7_out, A_out, G_out, CW);
input DIN;
input Reset;
input PB;
input clock;
output wire WR_MEM_out;
output wire DOUT_out;
output wire ADDR_out;
output wire DONE;
output wire IR_out;
output wire R0_out;
output wire R1_out;
output wire R2_out;
output wire R3_out;
output wire R4_out;
output wire R5_out;
output wire R6_out;
output wire R7_out;
output wire G_out;
output wire A_out;
//Control Wires
output wire CW;
wire gnz;
wire BusWires;
//Enables
wire R0_en, R1_en, R2_en, R3_en, R4_en, R5_en, R6_en, R7_en, A_en, G_en, IR_en;
wire ADD_SUB, COUNT_en, ADDR_en, DOUT_en, WR_MEM_en;
wire Mux_sel;
assign Mux_sel = CW;
assign R0_en = CW;
assign R1_en = CW;
assign R2_en = CW;
assign R3_en = CW;
assign R4_en = CW;
assign R5_en = CW;
assign R6_en = CW;
assign R7_en = CW;
assign A_en = CW;
assign G_en = CW;
assign IR_en = CW;
assign ADD_SUB = CW;
assign COUNT_en = CW;
assign ADDR_en = CW;
assign DOUT_en = CW;
assign WR_MEM_en = CW;
//Data not defined in output
wire ADD_SUB_out;
wire X_REG;
wire Y_REG;
//Instantiate Registers
registers R0(Reset, R0_en, clock, BusWires, R0_out);
registers R1(Reset, R1_en, clock, BusWires, R1_out);
registers R2(Reset, R2_en, clock, BusWires, R2_out);
registers R3(Reset, R3_en, clock, BusWires, R3_out);
registers R4(Reset, R4_en, clock, BusWires, R4_out);
registers R5(Reset, R5_en, clock, BusWires, R5_out);
registers R6(Reset, R6_en, clock, BusWires, R6_out);
registers_count R7(Reset, R7_en, COUNT_en, clock, BusWires, R7_out);
registers A(Reset, A_en, clock, BusWires, A_out);
register_g G(Reset, G_en, clock, ADD_SUB_out, G_out, gnz);
registers IR(Reset, IR_en, clock, DIN, IR_out);
registers ADDR(Reset, ADDR_en, clock, BusWires, ADDR_out);
registers DOUT(Reset, DOUT_en, clock, BusWires, DOUT_out);
flip_flop WR_MEM(Reset, clock, WR_MEM_en, WR_MEM_out);
add_sub stuff(A_out, BusWires, ADD_SUB, ADD_SUB_out);
data_mux mux(Mux_sel, R0_out, R1_out, R2_out, R3_out, R4_out, R5_out, R6_out, R7_out, DIN, G_out, BusWires);
three_to_8_decoder x_decoder(IR_out,X_REG);
three_to_8_decoder y_decoder(IR_out,Y_REG);
control M1(IR_out, X_REG, Y_REG, PB, Reset, clock, gnz, CW, DONE);
endmodule

`timescale 1 ps / 1 ps
module proc_testbench;
  wire PB; /* Run */
  wire Reset;
  wire enable; /* a generic write enable */
  wire wren;
  wire leden;
  wire done;
  wire clock;
  wire mem_out;
  wire address;
  wire dout;
  wire IR;
  wire REG0;
  wire REG1;
  wire REG2;
  wire REG3;
  wire REG4;
  wire REG5;
  wire REG6;
  wire PC; /* Register 7 */
  wire AR;
  wire GR;
  wire led_out; /* LED output */
  wire control;
  assign wren = (~address && ~address && ~address && ~address)?(enable):0;
  assign leden = (~address && ~address && ~address && ~address)?0:(enable);
  proc_gen StimulusGenerator (PB, Reset, clock);
  System DUV_1 (mem_out, Reset, PB, clock, enable, address, dout, done, IR, REG0, REG1, REG2, REG3, REG4, REG5, REG6, PC, AR, GR, control);
  irram DUV_2 (address, clock, dout, wren, mem_out);
  register_LED DUV_3 (Reset, leden, clock, dout, led_out);
  proc_check Checker (mem_out, Reset, PB, enable, wren, leden, done, clock, address, dout, control, done, IR, REG0, REG1, REG2, REG3, REG4, REG5, REG6, PC, AR, GR, led_out);
  
endmodule