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Altera_Forum
Honored Contributor
11 years agoMy Modelsim's version is DE 10.2a and the Quartus is 13.0sp1. All files are in .v and have the same port assignment style like the beginning. I was wondering should I use the Verilog-2001/Systemverilog style ports (ANSI) in these tools? If so, why error happens only in System module?
Thank you Dave! Yumeng