Modelsim Fatal error: "TOO MANY PORT CONNECTONS" Help me!

I made a simple testcase from the code shown and cannot reproduce your error. I was not correct about the illegal syntax.

Since I don't have your complete design, I can't say for sure that this is your problem. I would try commenting out all other code until you are left with just the code producing the error. Basically, comment out all other module instantiations.

The Verilog-2001 ANSI style port style I mentioned earlier is Verilog, no need for *.sv file extensions.

The Verilog-1995 non-ANSI style normally looks like

module name(port1,port2);
  input  port1;
  output  port2;
  wire  port1;
  reg  port2;
...
endmodule

Non-Ansi ports are declared at least twice, sometimes three times: the port name ordering, port direction, and port type. Your syntax has combined the port direction and port type.

Verilog-2001 ANSI style port combine all three declarations into one declaration.

module name(
  input  port1,
  output reg  port2
  );
...
endmodule