Modelsim Fatal error: "TOO MANY PORT CONNECTONS" Help me!

You are mixing Verilog-1995 style ports (non-ANSI) with Verilog-2001/Systemverilog style ports (ANSI). That syntax is not strictly legal. Try:

module System(
input wire  DIN,
input wire Reset,
input PB,
input clock,
output wire WR_MEM_out,
output wire DOUT_out,
output wire ADDR_out,
output wire DONE,
output wire IR_out,
output wire R0_out,
output wire R1_out,
output wire R2_out,
output wire R3_out,
output wire R4_out,
output wire R5_out,
output wire R6_out,
output wire R7_out,
output wire G_out,
output wire A_out,
//Control Wires
output wire CW
);

module System(
input wire  DIN,
      wire Reset, PB,clock,
output wire WR_MEM_out,
       wire  DOUT_out, ADDR_out,
       wire DONE,
       wire  IR_out, R0_out, R1_out, R2_out, R3_out, R4_out, R5_out, R6_out, R7_out, G_out, A_out,
//Control Wires
       wire CW
);