modelsim erro Unresolved defparam reference to 'dcfifo_component'

Question

Hi,

I'm back with FPGAs and I'm trying to simulate a simple FIFO from the standard IP catalogue for an Arria 10: 10AX115S3F45E2SG.

Because my job is a little part of a big project I have write down a code without pins specification, because for now I only want RTL simulation.

I have tested the test bench with my logic and it works, I can simulate it with modelsim but when I put the FIFO Modelsim complains, I attach the transcript at the end of the post.

I checked all the files that modelsim complains and are all there in the folder specified.

for information my configuration is:

Ubutnu-Mate 16.04

Quartus Prime 18.0 (with license)

Modelsim INTEL FPGA STARTER EDITION 10.5b

thanks for the help,

Guillermo

#   vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L  twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L twentynm -L  twentynm_hssi -L twentynm_hip -L rtl_work -L work -L  inputBuff2Clks_fifo_180 -voptargs="+acc"  Compactor_tb#  vsim -t 1ps  -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm_ver  -L twentynm_hssi_ver -L twentynm_hip_ver -L twentynm -L twentynm_hssi -L  twentynm_hip -L rtl_work -L work -L inputBuff2Clks_fifo_180  -voptargs=""+acc"" Compactor_tb #  Start time: 19:02:24 on Jun 28,2018#  Loading std.standard#  Loading std.textio(body)#  Loading ieee.std_logic_1164(body)#  Loading ieee.std_logic_textio(body)#  Loading work.compactor_tb(beha)#  Loading work.ut_compactor(beh)#  Loading work.ut_compactor_basic(beh)#  Loading ieee.numeric_std(body)#  Loading verilog.vl_types(body)#  Loading work.inputbuff2clks(rtl)#  Loading inputBuff2Clks_fifo_180.inputBuff2Clks_fifo_180_czaw2fq#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(69):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.enable_ecc.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(70):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.intended_device_family.#     Time: 0 ps  Iteration:  0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(71):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_hint.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(72):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_numwords.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(73):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_showahead.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(74):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_type.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(75):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_width.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(76):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_widthu.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(77):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.overflow_checking.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(78):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.rdsync_delaypipe.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(79):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.read_aclr_synch.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(80):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.underflow_checking.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(81):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.use_eab.#     Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(82):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.write_aclr_synch.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#   ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(83):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.wrsync_delaypipe.#     Time: 0 ps  Iteration: 0   Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v#  Loading work.elinkfromfile(beha)#  Error loading design#  Error: Error loading design#         Pausing macro execution#  MACRO ./compactorV01_run_msim_rtl_vhdl.do PAUSED at line 27

altera_forum · Answer

Hi,

--- Quote Start ---

I have tested the test bench with my logic and it works, I can simulate it with modelsim but when I put the FIFO Modelsim complains, I attach the transcript at the end of the post.

--- Quote End ---

Without code it is difficult to support, can you share your part of the code (after adding the FIFO & test bench)?

Since it was worked before adding FIFO, It might have an issue while instantiating the “dcfifo_component”.

Can you please refer the old thread & check any typo mistake, any missing port, signal declaration etc.

https://www.alteraforum.com/forum/showthread.php?t=55761

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

altera_forum · Answer

Have you generated the simulation models for the dcfifo that you created. If not, open the Qsys tool and generate the simulation models. Then include these simulation model sources also in your modelsim compilation flow. Now, it will find all of the required files and you will be able to simulate the design.

altera_forum · Answer

Hi,  "Vikas Jathar " : here is the code,  I thought it would be an error mostly related on libraries and Linux. I have searched for a typo in all the files generated by Quartus but I don't see nothing, but could be that I'm not recognizing the typo  "eapenabrm": In quartus 18 there is no more Qsys tool, now it's called platform designer, that said, If open it I don't know what to do, i didn't use it to create the code.  What I can says is that I've generated every thing from the IP catalog, all in vhdl. After answering this post I will try to do the same in verilogand I will post if there is any difference.  The forum is warning me that the post is too long so I put test bench and top level on another reply, but I it will take a little because I have to extract from top_level and testbench the part  dedicated to this.   
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity UT_Compactor_Basic is
	port(
		clkInStage		: in std_logic; --Only these signals are synched to clkInStage
		nReset			: in std_logic;
		elinkIn			: in std_logic_vector(23 downto 0);
		data_valid_in	: in std_logic;
		
		clkOutStage		: in std_logic; --Everything else is synched to that CLK.
		data_out		: out std_logic_vector(31 downto 0)
	);
END entity;
architecture beh of UT_Compactor_Basic is
	component InputClockDomainSync is
		port (
			CLKIn			: in std_logic; --Only these signals are synched to clkInStage
			nReset			: in std_logic;
			DataIn			: in std_logic_vector(23 downto 0);
			DataValidIn		: in std_logic;
			
			CLKOut			: in std_logic; --Everything else is synched to that CLK.
			DataOut			: out std_logic_vector(23 downto 0);
			DataValidOut	: out std_logic
		);
	end component InputClockDomainSync;
	
	component inputBuff2Clks is
		port (
			data    : in  std_logic_vector(23 downto 0); --  fifo_input.datain
			wrreq   : in  std_logic;                     --            .wrreq
			rdreq   : in  std_logic;                     --            .rdreq
			wrclk   : in  std_logic;                     --            .wrclk
			rdclk   : in  std_logic;                     --            .rdclk
			aclr    : in  std_logic;                     --            .aclr
			q       : out std_logic_vector(23 downto 0); -- fifo_output.dataout
			rdempty : out std_logic;                     --            .rdempty
			wrfull  : out std_logic                      --            .wrfull
		);
	end component inputBuff2Clks;
	
	signal newHeader : std_logic_vector(19 downto 0);
	signal newNumHits : std_logic_vector(5 downto 0);
	signal dataIn250 : std_logic_vector(23 downto 0);
	signal dataInValid250 : std_logic;
	
	signal wrfull,rdempty : std_logic;
begin
	data_out &lt;= "00000000" &amp; dataIn250;
	inBuffClkDomain : inputBuff2Clks port map (
		data    =&gt; elinkIn,    --  fifo_input.datain
		wrreq   =&gt; data_valid_in,   --            .wrreq
		rdreq   =&gt; '1',   --            .rdreq
		wrclk   =&gt; clkInStage,   --            .wrclk
		rdclk   =&gt; clkOutStage,   --            .rdclk
		aclr    =&gt; '0',    --            .aclr
		q       =&gt; dataIn250,       -- fifo_output.dataout
		rdempty =&gt; rdempty, --            .rdempty
		wrfull  =&gt; wrfull   --            .wrfull
	);
end beh;
   CODE GENERATED BY QUARTUS IP CATALOG   /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/synth/inputBuff2Clks_pkg.vhd 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package inputBuff2Clks_pkg is
	component inputBuff2Clks_fifo_180_czaw2fq is
		port (
			data    : in  std_logic_vector(23 downto 0) := (others =&gt; 'X'); -- datain
			wrreq   : in  std_logic                     := 'X';             -- wrreq
			rdreq   : in  std_logic                     := 'X';             -- rdreq
			wrclk   : in  std_logic                     := 'X';             -- wrclk
			rdclk   : in  std_logic                     := 'X';             -- rdclk
			aclr    : in  std_logic                     := 'X';             -- aclr
			q       : out std_logic_vector(23 downto 0);                    -- dataout
			rdempty : out std_logic;                                        -- rdempty
			wrfull  : out std_logic                                         -- wrfull
		);
	end component inputBuff2Clks_fifo_180_czaw2fq;
end inputBuff2Clks_pkg;
   /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/synth/inputBuff2Clks.vhd 
-- inputBuff2Clks.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
library inputBuff2Clks_fifo_180;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use inputBuff2Clks_fifo_180.inputBuff2Clks_pkg.all;
entity inputBuff2Clks is
	port (
		data    : in  std_logic_vector(23 downto 0) := (others =&gt; '0'); --  fifo_input.datain
		wrreq   : in  std_logic                     := '0';             --            .wrreq
		rdreq   : in  std_logic                     := '0';             --            .rdreq
		wrclk   : in  std_logic                     := '0';             --            .wrclk
		rdclk   : in  std_logic                     := '0';             --            .rdclk
		aclr    : in  std_logic                     := '0';             --            .aclr
		q       : out std_logic_vector(23 downto 0);                    -- fifo_output.dataout
		rdempty : out std_logic;                                        --            .rdempty
		wrfull  : out std_logic                                         --            .wrfull
	);
end entity inputBuff2Clks;
architecture rtl of inputBuff2Clks is
begin
	fifo_0 : component inputBuff2Clks_fifo_180.inputBuff2Clks_pkg.inputBuff2Clks_fifo_180_czaw2fq
		port map (
			data    =&gt; data,    --  fifo_input.datain
			wrreq   =&gt; wrreq,   --            .wrreq
			rdreq   =&gt; rdreq,   --            .rdreq
			wrclk   =&gt; wrclk,   --            .wrclk
			rdclk   =&gt; rdclk,   --            .rdclk
			aclr    =&gt; aclr,    --            .aclr
			q       =&gt; q,       -- fifo_output.dataout
			rdempty =&gt; rdempty, --            .rdempty
			wrfull  =&gt; wrfull   --            .wrfull
		);
end architecture rtl; -- of inputBuff2Clks
  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/synth/inputBuff2Clks_fifo_180_czaw2fq.v 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module  inputBuff2Clks_fifo_180_czaw2fq  (
    aclr,
    data,
    rdclk,
    rdreq,
    wrclk,
    wrreq,
    q,
    rdempty,
    wrfull);
    input    aclr;
    input    data;
    input    rdclk;
    input    rdreq;
    input    wrclk;
    input    wrreq;
    output   q;
    output   rdempty;
    output   wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri0     aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
    wire  sub_wire0;
    wire  sub_wire1;
    wire  sub_wire2;
    wire  q = sub_wire0;
    wire  rdempty = sub_wire1;
    wire  wrfull = sub_wire2;
    dcfifo  dcfifo_component (
                .aclr (aclr),
                .data (data),
                .rdclk (rdclk),
                .rdreq (rdreq),
                .wrclk (wrclk),
                .wrreq (wrreq),
                .q (sub_wire0),
                .rdempty (sub_wire1),
                .wrfull (sub_wire2),
                .eccstatus (),
                .rdfull (),
                .rdusedw (),
                .wrempty (),
                .wrusedw ());
    defparam
        dcfifo_component.enable_ecc  = "FALSE",
        dcfifo_component.intended_device_family  = "Arria 10",
        dcfifo_component.lpm_hint  = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
        dcfifo_component.lpm_numwords  = 4,
        dcfifo_component.lpm_showahead  = "OFF",
        dcfifo_component.lpm_type  = "dcfifo",
        dcfifo_component.lpm_width  = 24,
        dcfifo_component.lpm_widthu  = 2,
        dcfifo_component.overflow_checking  = "ON",
        dcfifo_component.rdsync_delaypipe  = 5,
        dcfifo_component.read_aclr_synch  = "OFF",
        dcfifo_component.underflow_checking  = "ON",
        dcfifo_component.use_eab  = "ON",
        dcfifo_component.write_aclr_synch  = "OFF",
        dcfifo_component.wrsync_delaypipe  = 5;
endmodule

altera_forum · Answer

Try to add -L altera_mf_ver to command-line options, before -L altera_mf.

altera_forum · Answer

eugenek, where I have to put this line?  Also, could this be a problem with licenses?

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modelsim erro Unresolved defparam reference to 'dcfifo_component'

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