Honored Contributor
Honored ContributorHi,
"Vikas Jathar " : here is the code, I thought it would be an error mostly related on libraries and Linux. I have searched for a typo in all the files generated by Quartus but I don't see nothing, but could be that I'm not recognizing the typo "eapenabrm": In quartus 18 there is no more Qsys tool, now it's called platform designer, that said, If open it I don't know what to do, i didn't use it to create the code. What I can says is that I've generated every thing from the IP catalog, all in vhdl. After answering this post I will try to do the same in verilogand I will post if there is any difference. The forum is warning me that the post is too long so I put test bench and top level on another reply, but I it will take a little because I have to extract from top_level and testbench the part dedicated to this.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity UT_Compactor_Basic is
port(
clkInStage : in std_logic; --Only these signals are synched to clkInStage
nReset : in std_logic;
elinkIn : in std_logic_vector(23 downto 0);
data_valid_in : in std_logic;
clkOutStage : in std_logic; --Everything else is synched to that CLK.
data_out : out std_logic_vector(31 downto 0)
);
END entity;
architecture beh of UT_Compactor_Basic is
component InputClockDomainSync is
port (
CLKIn : in std_logic; --Only these signals are synched to clkInStage
nReset : in std_logic;
DataIn : in std_logic_vector(23 downto 0);
DataValidIn : in std_logic;
CLKOut : in std_logic; --Everything else is synched to that CLK.
DataOut : out std_logic_vector(23 downto 0);
DataValidOut : out std_logic
);
end component InputClockDomainSync;
component inputBuff2Clks is
port (
data : in std_logic_vector(23 downto 0); -- fifo_input.datain
wrreq : in std_logic; -- .wrreq
rdreq : in std_logic; -- .rdreq
wrclk : in std_logic; -- .wrclk
rdclk : in std_logic; -- .rdclk
aclr : in std_logic; -- .aclr
q : out std_logic_vector(23 downto 0); -- fifo_output.dataout
rdempty : out std_logic; -- .rdempty
wrfull : out std_logic -- .wrfull
);
end component inputBuff2Clks;
signal newHeader : std_logic_vector(19 downto 0);
signal newNumHits : std_logic_vector(5 downto 0);
signal dataIn250 : std_logic_vector(23 downto 0);
signal dataInValid250 : std_logic;
signal wrfull,rdempty : std_logic;
begin
data_out <= "00000000" & dataIn250;
inBuffClkDomain : inputBuff2Clks port map (
data => elinkIn, -- fifo_input.datain
wrreq => data_valid_in, -- .wrreq
rdreq => '1', -- .rdreq
wrclk => clkInStage, -- .wrclk
rdclk => clkOutStage, -- .rdclk
aclr => '0', -- .aclr
q => dataIn250, -- fifo_output.dataout
rdempty => rdempty, -- .rdempty
wrfull => wrfull -- .wrfull
);
end beh;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package inputBuff2Clks_pkg is
component inputBuff2Clks_fifo_180_czaw2fq is
port (
data : in std_logic_vector(23 downto 0) := (others => 'X'); -- datain
wrreq : in std_logic := 'X'; -- wrreq
rdreq : in std_logic := 'X'; -- rdreq
wrclk : in std_logic := 'X'; -- wrclk
rdclk : in std_logic := 'X'; -- rdclk
aclr : in std_logic := 'X'; -- aclr
q : out std_logic_vector(23 downto 0); -- dataout
rdempty : out std_logic; -- rdempty
wrfull : out std_logic -- wrfull
);
end component inputBuff2Clks_fifo_180_czaw2fq;
end inputBuff2Clks_pkg;
-- inputBuff2Clks.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
library inputBuff2Clks_fifo_180;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use inputBuff2Clks_fifo_180.inputBuff2Clks_pkg.all;
entity inputBuff2Clks is
port (
data : in std_logic_vector(23 downto 0) := (others => '0'); -- fifo_input.datain
wrreq : in std_logic := '0'; -- .wrreq
rdreq : in std_logic := '0'; -- .rdreq
wrclk : in std_logic := '0'; -- .wrclk
rdclk : in std_logic := '0'; -- .rdclk
aclr : in std_logic := '0'; -- .aclr
q : out std_logic_vector(23 downto 0); -- fifo_output.dataout
rdempty : out std_logic; -- .rdempty
wrfull : out std_logic -- .wrfull
);
end entity inputBuff2Clks;
architecture rtl of inputBuff2Clks is
begin
fifo_0 : component inputBuff2Clks_fifo_180.inputBuff2Clks_pkg.inputBuff2Clks_fifo_180_czaw2fq
port map (
data => data, -- fifo_input.datain
wrreq => wrreq, -- .wrreq
rdreq => rdreq, -- .rdreq
wrclk => wrclk, -- .wrclk
rdclk => rdclk, -- .rdclk
aclr => aclr, -- .aclr
q => q, -- fifo_output.dataout
rdempty => rdempty, -- .rdempty
wrfull => wrfull -- .wrfull
);
end architecture rtl; -- of inputBuff2Clks
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module inputBuff2Clks_fifo_180_czaw2fq (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire q = sub_wire0;
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.enable_ecc = "FALSE",
dcfifo_component.intended_device_family = "Arria 10",
dcfifo_component.lpm_hint = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 24,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
