Forum Discussion
Ftiglius
New Contributor
7 years agoHI! I meet same error simulating a dcfifo 16 bit to 8 bit, 32 words deep.
I insert suggested option -L altera_mf_ver on .do file that Modelsim reads to launch simulation, but it doesnt' work. Same errors!
There is any workaround to simulate it ?? (Quartus prime 18.0, Modelsim INTEL FPGA STARTER EDITION 10.5b..
Thanks for any suggestion!