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Altera_Forum's avatar
Altera_Forum
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17 years ago

modelsim analog waveform transients

I'm using modelsim-Altera to make a gate-level simulation of an own ifft core, the target platform is an Stratix II FPGA.

When i select the analog waveform display format for a signed 16 bits port corresponding to a Synthesized sine wave , i get in the picture some peaks (like glitches) that take random and big values, however the sine wave has an amplitude of 64. The basic sine shape looks well. I notice that this peaks appear before the t_su completion.

I tried with a RTL simulation, however the ram memories in design (m4k's and m512's) don't work well.

There is a way to define a trigger source, Such that the analog waveform display is sampled after every rising edge of a clock signal?.

Why the ram memories don't work in the RTL-simulation?

I appreciate any help with this.

Regards,

Alex Parrado

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think, the glitches in analog waveforms are corresponding to glitches in the displayed signal. Resampling the data before displaying them should help.

    I performed RTL and gate-level simulations of designs with RAM blocks and wasn't aware of any ModelSim issues in this regard. What do you mean with don't work well?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    i run the rtl-level simulation and de data before the memories ports is correct, after of them the data is wrong. modelsim shows a warning referring to the clock edge in that the reading is made.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I didn't exactly understand what's the timing problem releated to memory operation. But if the data is stable a the clock edge, I meant you can simply add a register in your simulation, clocked from the said clock.

    The user manual tells about an option to sample signals at a clock edge, but I'm not sure if it applies only to the list window or also to the waveform window.