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Altera_Forum
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17 years ago

modelsim analog waveform transients

I'm using modelsim-Altera to make a gate-level simulation of an own ifft core, the target platform is an Stratix II FPGA. When i select the analog waveform display format for a signed 16 bits ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

i run the rtl-level simulation and de data before the memories ports is correct, after of them the data is wrong. modelsim shows a warning referring to the clock edge in that the reading is made.