Modelsim-Altera errors

Question

My design incorporates a PLL that I phase shift to be 180 degrees off-phase to another clock with the same frequency. The phase shift is done by a pll_reconfig block.

When I run gate level simulation in modelsim-altera it seems to work just fine but suddenly after a while the signals turn red and I receive the following error:

# ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3614784 ps, datain:3614950 ps, 200 ps );# Time: 3614950 ps Iteration: 0 Instance: /tb_top/top_i/\ch0_i|clk_optimizer_i|phase_shift # ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3614784 ps, datain:3614954 ps, 200 ps );# Time: 3614954 ps Iteration: 0 Instance: /tb_top/top_i/\ch0_i|clk_optimizer_i|fsm_state.STATE_DONE # ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3614784 ps, datain:3614958 ps, 200 ps );# Time: 3614958 ps Iteration: 0 Instance: /tb_top/top_i/\ch0_i|clk_optimizer_i|fsm_state.STATE_ADJUST # ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3630889 ps, datain:3630907 ps, 200 ps );# Time: 3630907 ps Iteration: 0 Instance: /tb_top/top_i/\ch1_i|clk_optimizer_i|fsm_state.STATE_ADJUST # ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3630889 ps, datain:3630918 ps, 200 ps );# Time: 3630918 ps Iteration: 0 Instance: /tb_top/top_i/\ch1_i|clk_optimizer_i|fsm_state.STATE_DONE # ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3630889 ps, datain:3630918 ps, 200 ps );# Time: 3630918 ps Iteration: 0 Instance: /tb_top/top_i/\ch1_i|clk_optimizer_i|phase_shift

The errors aren't very intuitive as to their meaning, anyone who knows what they mean?

altera_forum · Answer

The module that does the re-programming of the pll looks like this, and it's the parameters in this module that the errors refer to. module clk_optimizer(
  // System reset
  input reset_n,
  
  // Tx clock, not phase adjustable
  input tx_clk,
  
  // Rx clock, phase adjustable
  input rx_clk,
  
  // PLL reconfiguration I/F
  input  busy,
  input  locked,
  output reg phase_shift,
  output reg direction,
  
  // Status/Control
  input  realign,
  output reg done);
  
  // ==========================================================================
  // FSM states
  // ==========================================================================
  parameter  
    STATE_DECIDE = 2'h0,
    STATE_ADJUST = 2'h1,
    STATE_DONE   = 2'h2,
    STATE_DUMMY3 = 2'h3;
  reg  fsm_state;
  
  always @(posedge tx_clk, negedge reset_n) begin
    if (!reset_n) begin
      fsm_state   &lt;= STATE_DECIDE;
      done        &lt;= 0;
      phase_shift &lt;= 0;
      direction   &lt;= 0;
    end else begin
      // FSM
      case (fsm_state)
        STATE_DECIDE: begin
          if (locked &amp;&amp; !busy) begin
            fsm_state &lt;= STATE_ADJUST;
            direction &lt;= !rx_clk; // rx_clk would phase-align
          end
        end
        
        STATE_ADJUST: begin
          if (locked &amp;&amp; !busy &amp;&amp; !phase_shift) begin
            if (rx_clk == !direction) begin // Still too early/late
              phase_shift &lt;= 1;
            end else begin
              fsm_state &lt;= STATE_DONE;
            end
          end else begin
            phase_shift &lt;= 0;
          end
        end
          
        STATE_DONE: begin
          if (locked &amp;&amp; !busy) begin
            if (realign) begin
              fsm_state &lt;= STATE_DECIDE;
              done &lt;= 0;
            end else begin
              done &lt;= 1;
            end
          end
        end
        
        default: begin
          fsm_state &lt;= STATE_DECIDE;
        end
      endcase
    end
  end
  
endmodule

altera_forum · Answer

--- Quote Start ---  The module that does the re-programming of the pll looks like this, and it's the parameters in this module that the errors refer to. module clk_optimizer(
  // System reset
  input reset_n,
  
  // Tx clock, not phase adjustable
  input tx_clk,
  
  // Rx clock, phase adjustable
  input rx_clk,
  
  // PLL reconfiguration I/F
  input  busy,
  input  locked,
  output reg phase_shift,
  output reg direction,
  
  // Status/Control
  input  realign,
  output reg done);
  
  // ==========================================================================
  // FSM states
  // ==========================================================================
  parameter  
    STATE_DECIDE = 2'h0,
    STATE_ADJUST = 2'h1,
    STATE_DONE   = 2'h2,
    STATE_DUMMY3 = 2'h3;
  reg  fsm_state;
  
  always @(posedge tx_clk, negedge reset_n) begin
    if (!reset_n) begin
      fsm_state   &lt;= STATE_DECIDE;
      done        &lt;= 0;
      phase_shift &lt;= 0;
      direction   &lt;= 0;
    end else begin
      // FSM
      case (fsm_state)
        STATE_DECIDE: begin
          if (locked &amp;&amp; !busy) begin
            fsm_state &lt;= STATE_ADJUST;
            direction &lt;= !rx_clk; // rx_clk would phase-align
          end
        end
        
        STATE_ADJUST: begin
          if (locked &amp;&amp; !busy &amp;&amp; !phase_shift) begin
            if (rx_clk == !direction) begin // Still too early/late
              phase_shift &lt;= 1;
            end else begin
              fsm_state &lt;= STATE_DONE;
            end
          end else begin
            phase_shift &lt;= 0;
          end
        end
          
        STATE_DONE: begin
          if (locked &amp;&amp; !busy) begin
            if (realign) begin
              fsm_state &lt;= STATE_DECIDE;
              done &lt;= 0;
            end else begin
              done &lt;= 1;
            end
          end
        end
        
        default: begin
          fsm_state &lt;= STATE_DECIDE;
        end
      endcase
    end
  end
  
endmodule  --- Quote End ---     Hi,  for me it looks like that you have timing violations in your design. Did you run a timing analysis in Quartus ?  Kind regards  GPK

altera_forum · Answer

Thanks for your reply, I do have timing violations it seems. Are these types of error messages a normal indication of timing violations?

altera_forum · Answer

--- Quote Start ---

Thanks for your reply, I do have timing violations it seems. Are these types of error messages a normal indication of timing violations?

--- Quote End ---

Hi,

yes, in a simulator you will get such or similar messages for timing violations.

# ** Error: C:/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1655): $hold( posedge clk &&& nosloadsclr:3614784 ps, datain:3614950 ps, 200 ps );

This messages indicates that you have a holdtime violation.

Your Clock edge occurs at simulation time 3614784 ps

Your data changed at 3614950 ps, that is 166ps behind the clockedge. Require are 200ps.

You have a time violation of 34ps.

Is this a path in your design ?

Kind regards

GPK

altera_forum · Answer

Well this is actually a desired behavior. I have two clocks in this block tx_clk and rx_clk and I sample rx_clk on rising edge of tx_clk and phase shift rx_clk until it changes value. This (theoretically at least) gives me a 180 degrees phase difference between the two which is exactly what I want.

How would I go about setting a constraint that tells quartus that this is ok?

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Modelsim-Altera errors

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