Modelsim-Altera errors

The module that does the re-programming of the pll looks like this, and it's the parameters in this module that the errors refer to.

module clk_optimizer(
  // System reset
  input reset_n,
  
  // Tx clock, not phase adjustable
  input tx_clk,
  
  // Rx clock, phase adjustable
  input rx_clk,
  
  // PLL reconfiguration I/F
  input  busy,
  input  locked,
  output reg phase_shift,
  output reg direction,
  
  // Status/Control
  input  realign,
  output reg done);
  
  // ==========================================================================
  // FSM states
  // ==========================================================================
  parameter  
    STATE_DECIDE = 2'h0,
    STATE_ADJUST = 2'h1,
    STATE_DONE   = 2'h2,
    STATE_DUMMY3 = 2'h3;
  reg  fsm_state;
  
  always @(posedge tx_clk, negedge reset_n) begin
    if (!reset_n) begin
      fsm_state   <= STATE_DECIDE;
      done        <= 0;
      phase_shift <= 0;
      direction   <= 0;
    end else begin
      // FSM
      case (fsm_state)
        STATE_DECIDE: begin
          if (locked && !busy) begin
            fsm_state <= STATE_ADJUST;
            direction <= !rx_clk; // rx_clk would phase-align
          end
        end
        
        STATE_ADJUST: begin
          if (locked && !busy && !phase_shift) begin
            if (rx_clk == !direction) begin // Still too early/late
              phase_shift <= 1;
            end else begin
              fsm_state <= STATE_DONE;
            end
          end else begin
            phase_shift <= 0;
          end
        end
          
        STATE_DONE: begin
          if (locked && !busy) begin
            if (realign) begin
              fsm_state <= STATE_DECIDE;
              done <= 0;
            end else begin
              done <= 1;
            end
          end
        end
        
        default: begin
          fsm_state <= STATE_DECIDE;
        end
      endcase
    end
  end
  
endmodule