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Altera_Forum
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16 years ago

Modelsim-Altera errors

My design incorporates a PLL that I phase shift to be 180 degrees off-phase to another clock with the same frequency. The phase shift is done by a pll_reconfig block. When I run gate level simu...
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Altera_Forum
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16 years ago

RX_CLOCK REGION

===[10 Gbit/s serial optical data]===> Opto-demux ===[16bit@622MHz]===> FPGA-LVDS_RX, PLL ===[128bit@77MHz]===>

TX_CLOCK REGION

mirror of above except that the transmission clock (622 MHz) is fed from the same opto-mux circuit. This is used in a Fast PLL in the FPGA to have another 77 MHz clock.

The two 77 MHz clocks are the ones referred to above, once the PLLs have locked they will have the exact same frequency but unknown phase shift between each other. This is to make sure that the transmission of data between the two internal clock regions won't cause issues due to the clock edges being too close.