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Altera_Forum
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16 years ago

Modelsim-Altera errors

My design incorporates a PLL that I phase shift to be 180 degrees off-phase to another clock with the same frequency. The phase shift is done by a pll_reconfig block. When I run gate level simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Well this is actually a desired behavior. I have two clocks in this block tx_clk and rx_clk and I sample rx_clk on rising edge of tx_clk and phase shift rx_clk until it changes value. This (theoretically at least) gives me a 180 degrees phase difference between the two which is exactly what I want.

How would I go about setting a constraint that tells quartus that this is ok?

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Hi,

maybe I missed something, but why couldn't you use the inverted tx_clk?

Kind regards

GPK