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Altera_Forum
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15 years ago

Minimum Pulse Width timing violation

Hello! I tried to make simple test project which simulates interface with ADC. It should receive 423 MHz data (12 bit) with DDR clock (211.5 MHz). I use PLL to double input frequency (true DDR sampling is inconvenient here due to some ADCs properties). Target device is Cyclone-4, speed grade -6.

It successfully compiles but timing is not met.

Slow timing models are ok but Fast Timing models fails for Minimum Pulse Width parameter of 423 Mhz clock (for all dffs connected to this clock).

As one can see (see attachment), actual timing 2.364 ns corresponds to used 423 MHz frequency. But requirement is 2.899 ns (it equal to 345 MHz). I checked data sheet and did not found such limitations. Slow timing models have requirements 2.000 ns (500 MHz) for respective parameter which corresponds to clock tree switch limit.

Unfortunately, I'm not familiar with TimeQuest Timing Analyzer. Can anyone explain what problem here and how it can be fixed? Thank you.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I can't see why you use 423MHz inside cyclone. I think it is way too high.

    I believe you should stick to 211.5 with two parallel channels (odd/even) until the point where your samplingrate drops to half or so.

    Minimum pulse width violation got nothing to do with register timing violation and hence is not related directly to fmax. It is entirely a new violation of very fast clocks or gated clocks that suffer glitches (I believe glitches do not apply in your case)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    File an SR. Usually it's the clock tree that's the problem, but you're right that it's spec'd a lot higher.

    That being said, it would probably make sense to architect as a DDR interface and feed it with a 211.5MHz clock. Naturally that would remove the problem. I'm sure you're bringing it down to that rate or slower anyway.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, I agree. Structure above is one of possible structures which was analyzed. I decide to refuse it.

    DDR structure (with ALTDDIO) works correctly. But problem is still here: what limits my design to 345 MHz (2.899 ns) whereas Altera declares 500 MHz limit for Cyclone 4?

    (I checked that my test DDR design have same limit 2.899 ns for Fast 0C model)