Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Minimum Pulse Width timing violation

Hello! I tried to make simple test project which simulates interface with ADC. It should receive 423 MHz data (12 bit) with DDR clock (211.5 MHz). I use PLL to double input frequency (true DDR sampli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, I agree. Structure above is one of possible structures which was analyzed. I decide to refuse it.

DDR structure (with ALTDDIO) works correctly. But problem is still here: what limits my design to 345 MHz (2.899 ns) whereas Altera declares 500 MHz limit for Cyclone 4?

(I checked that my test DDR design have same limit 2.899 ns for Fast 0C model)