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Altera_Forum's avatar
Altera_Forum
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15 years ago

Minimum Pulse Width timing violation

Hello! I tried to make simple test project which simulates interface with ADC. It should receive 423 MHz data (12 bit) with DDR clock (211.5 MHz). I use PLL to double input frequency (true DDR sampli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

File an SR. Usually it's the clock tree that's the problem, but you're right that it's spec'd a lot higher.

That being said, it would probably make sense to architect as a DDR interface and feed it with a 211.5MHz clock. Naturally that would remove the problem. I'm sure you're bringing it down to that rate or slower anyway.