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Altera_Forum
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15 years ago

Minimum Pulse Width timing violation

Hello! I tried to make simple test project which simulates interface with ADC. It should receive 423 MHz data (12 bit) with DDR clock (211.5 MHz). I use PLL to double input frequency (true DDR sampli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I can't see why you use 423MHz inside cyclone. I think it is way too high.

I believe you should stick to 211.5 with two parallel channels (odd/even) until the point where your samplingrate drops to half or so.

Minimum pulse width violation got nothing to do with register timing violation and hence is not related directly to fmax. It is entirely a new violation of very fast clocks or gated clocks that suffer glitches (I believe glitches do not apply in your case)