New ContributorMerge simplex transceiver (tx and rx lanes) PHYs in Quartus® Prime Platform Designer on Agilex F014
Hi,
I'm trying to allocate a 8 lanes tx and a 4 lanes rx in the E-tile bank 9A connecting to the same QSFPDD1 (8 pins for tx_serial[] output ports and 4 pins for rx_serial[] output ports) as shown in the figure 1. Since by default, when using IP JESD204C simplex transmitter and receiver IPs, the coupled-pair rx or tx channel are tied off, I want to merge multiple jesd204C IP blocks to maximize transceiver channel utilization. I used wire-level connections in platform designer to allow the transceiver TX and RX PHYs to share the same address space, figure 2 ( https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/hsio/2020/how-do-i-merge-simplex-transceiver-phys-inside-the-intel--quartu.html ) and also I added XCVR_RECONFIG_GROUP in the QSF assignments as follows:
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx_serial_data[0] set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx_serial_data[1] set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to rx_serial_data[2] set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to rx_serial_data[3] set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx_serial_data_n[0] set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx_serial_data_n[1] set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to rx_serial_data_n[2] set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to rx_serial_data_n[3] set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx_serial_data[0] set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx_serial_data[1] set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to tx_serial_data[2] set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to tx_serial_data[3] set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to tx_serial_data[4] set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to tx_serial_data[5] set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to tx_serial_data[6] set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to tx_serial_data[7] set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx_serial_data_n[0] set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx_serial_data_n[1] set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to tx_serial_data_n[2] set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to tx_serial_data_n[3] set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to tx_serial_data_n[4] set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to tx_serial_data_n[5] set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to tx_serial_data_n[6] set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to tx_serial_data_n[7]
(chapter 6.14 in
The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 HSSI_C3_DUPLEX_CHANNEL_CLUSTER(s)). The Fitter cannot place logic HSSI_C3_DUPLEX_CHANNEL_CLUSTER that is part of JESD204C Intel FPGA IP j204c_tx_ip_intel_jesd204c_intel_jesd204c_110_cs5x7ii in region (332, 0) to (334, 111), to which it is constrained, because there are no valid locations in the region for logic of this type. No legal location could be found out of 1 considered location(s). Location(s) already occupied and components cannot be merged.
The error seems to be when merging the 8 TX pins with the 4 RX pins, it failed, causing the 4 merging conflicts.
One thing I notice that looks weird is the Address map (figure 3). The address for j204c_tx_ip.intel_jesd204c_j204c_reconfig and j204c_rx_ip.intel_jesd204c_j204c_reconfig, ranges are 0x0000_0000 - 0x0000_0000 and 0x0000_0001 - 0x0000_0001 respectively.
Is there anything I miss when merging 2 simplex PHYs? Any help would be appreciated.
