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Winston_Sun's avatar
Winston_Sun
Icon for New Contributor rankNew Contributor
5 years ago

Merge simplex transceiver (tx and rx lanes) PHYs in Quartus® Prime Platform Designer on Agilex F014

Hi, I'm trying to allocate a 8 lanes tx and a 4 lanes rx in the E-tile bank 9A connecting to the same QSFPDD1 (8 pins for tx_serial[] output ports and 4 pins for rx_serial[] output ports) as shown ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, you have some inquiries merging of simplex instances. Based on my understanding, the two instance will need to be of the same number of channel. To facilitate the debugging, I would recommend you to start with two 4 channels simplex instances in RTL and try on the merging. Once it is successful, you may move to Platform Designer to try out merging. This would be helpful to narrow down issues if there is any arise.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin


  • Winston_Sun's avatar
    Winston_Sun
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Chee,

    I tried merging simplex transmitter and receiver PHY (4T4R) and it still gives the same error about pin conflicts. In page 37 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf , it says "For simplex variants with E-tile transceiver, the underneath transceiver is in duplex mode. The merging of independent TX and RX within a transceiver channel is not supported in this version",

    Does Agilex E-tile supports merging simplex jesd204c transmitter and receiver PHY in the first place? If yes, is there any example designs or documents I can refer to?

    Thanks,

    Winston