Forum Discussion

Winston_Sun's avatar
Winston_Sun
Icon for New Contributor rankNew Contributor
6 years ago

Merge simplex transceiver (tx and rx lanes) PHYs in Quartus® Prime Platform Designer on Agilex F014

Hi, I'm trying to allocate a 8 lanes tx and a 4 lanes rx in the E-tile bank 9A connecting to the same QSFPDD1 (8 pins for tx_serial[] output ports and 4 pins for rx_serial[] output ports) as shown ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Winston,


Sorry for the delay. I might have overlooked the notification from your previous post. Sorry for the inconvenience.


Regarding your inquiries on the device support, yes, your understanding is correct. JESD204C is currently supported in E-Tile only.