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Winston_Sun's avatar
Winston_Sun
Icon for New Contributor rankNew Contributor
5 years ago

Merge simplex transceiver (tx and rx lanes) PHYs in Quartus® Prime Platform Designer on Agilex F014

Hi, I'm trying to allocate a 8 lanes tx and a 4 lanes rx in the E-tile bank 9A connecting to the same QSFPDD1 (8 pins for tx_serial[] output ports and 4 pins for rx_serial[] output ports) as shown ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Winston,


Thanks for your update and clarification that you are using E-Tile transceivers. For your information, due to the underneath architecture, when E-Tile is put to simplex mode, the unused pair (TX or RX) will be powered down. This restriction is tile dependent. Therefore, in the Agilex E-tile, similar restriction should apply. Sorry for the inconvenience. As a workaround, you might want to explore H-Tile if you merging is required.

Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


Winston_Sun's avatar
Winston_Sun
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5 years ago

Hi Chee,

Thanks for your clarification! One more question, when I read the JESD204C intel IP document, it says that Device Support on the JESD204C is Agilex (e-tile) or Stratix 10 (e-tile), shown in the attached screenshot. Does this mean that I cannot use H-tiles for JESD204C? So I can only pick either to merge simplex PHY (H-tiles) or using JESD204C IP block (E-tiles)?

Thanks again,

Winston