MAX10 LVDS Output Issue in one Single Differential Pair

Hi,

We are using the MAX10M08SAE144I7G and have a problem with a specific LVDS output pin.

The signals A and C, which use pins 38, 39 and 57, 58, show correct LVDS signals on the oscilloscope. However, for signal B, using pins 44 and 45, we observe like two single-ended signals with the same phase instead of a proper LVDS signal. (Using 100 ohm termination)

All three differential pairs are from the same bank (bank 3 on bottom), which supports true LVDS output. Bank 3 is powered with 2.5V.

Even when we declare only signal B, it still doesn’t work.

We tested the same firmware on the MAX 10 10M08 Eval Kit Board, which uses the MAX10M08SAE144C8G FPGA, and signal B works correctly in true LVDS.

Thanks,

Albert E.