MAX10 (10M50DAF484C8G): Maximum Frequency for CLK In, CLK Out, and GPIO Pins"

Hi Pooja,

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

For the CLK In and CLK Out, can you confirm which frequency do you meant? Is it for the internal oscillator? If yes, refer below link:

https://www.intel.com/content/www/us/en/docs/programmable/683794/current/internal-oscillator-specifications.html

Regards,

Aqid

Hi,

Can the maximum frequency of pll_clk_out be 100 MHz? Is it possible to output a 100 MHz from it? Similarly, can we drive the GPIO pins with a 100 MHz signal?

Thank you

Hi,

Based on the MAX 10 datasheet for PLL specifications, PLL output frequency for external clock output can go up to 472.5 MHz. However, this parameter is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

Regards,

Aqid

Hi,

I wish to follow up, do you need more support on this?

Regards,

Aqid

Hi Aqid,

Can you please tell the maximum frequency for 1.8-V LVCMOS I/O standard?

Thank you

Hi,

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Just so you know, actual achievable frequency depends on design and system-specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

Link for IBIS Model:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html

Regards,

Aqid

I wish to follow up with you.

Do you have any more concerns on this question before I close this thread?

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